1 data sheet acquired from harris semiconductor schs140e features asynchronous set and reset schmitt trigger clock inputs typical f max = 54mhz at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh pinout cd54hc109, cd54hct109 (cerdip) cd74hc109, CD74HCT109 (pdip, soic) top view description the ?c109 and ?ct109 are dual j- k ?p-?ps with set and reset. the ?p-?p changes state with the positive transition of clock (1cp and 2cp). the ?p-?p is set and reset by active-low s and r, respectively. a low on both the set and reset inputs simultaneously will force both q and q outputs high. however, both set and reset going high simultaneously results in an unpredictable output condition. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1r 1j 1k 1cp 1s 1q gnd 1q v cc 2j 2k 2cp 2s 2q 2q 2r ordering information part number temp. range ( o c) package cd54hc109f3a -55 to 125 16 ld cerdip cd54hct109f3a -55 to 125 16 ld cerdip cd74hc109e -55 to 125 16 ld pdip cd74hc109m -55 to 125 16 ld soic cd74hc109mt -55 to 125 16 ld soic cd74hc109m96 -55 to 125 16 ld soic CD74HCT109e -55 to 125 16 ld pdip CD74HCT109m -55 to 125 16 ld soic CD74HCT109mt -55 to 125 16 ld soic CD74HCT109m96 -55 to 125 16 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. march 1998 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc109, cd74hc109, cd54hct109, CD74HCT109 dual j- k flip-flop with set and reset positive-edge trigger [ /title ( cd74h c 109, c d74h c t109) / subject ( dual j- k flip- f lop w ith set a nd r eset
2 functional diagram logic diagram truth table inputs outputs s rcpj kq q lhxxxhl h l xxxlh l l x x x h (note 1) h (note 1) h h lllh h h h l toggle hh l h no change hh hhhl h h l x x no change h= high level (steady state) l= low level (steady state) x= don? care = low-to-high transition note: 1. unpredictable and unstable condition if both s and r go high simultaneously 1s 2s 2 r 5 11 6 7 1 q 1q 15 1 1r 2k 13 12 10 9 2 q 2q 2cp f/f 1 f/f 2 gnd = 8 v cc = 16 2j 14 1k 3 4 1cp 1j 2 s j k cl cl r q q 6(10) 7(9) q q 5(11) s 2(14) j 3(13) k 4(12) cp 1(15) r ff v cc gnd 16 8 cd54hc109, cd74hc109, cd54hct109, CD74HCT109
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc c p input rise and fall time, t r , t f 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) input rise and fall time (all inputs except c p ), t r , t f 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 2) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 2. the package thermal impedance is calculated in accordance with jesd 51-7 dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v 4.5 4.4 - - 4.4 - 4.4 - v 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.96 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v cd54hc109, cd74hc109, cd54hct109, CD74HCT109
4 low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 4.5 - - 0.1 - 0.1 - 0.1 v 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 4 - 40 - 80 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd - 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 4 - 40 - 80 a additional quiescent device current per input pin: 1 unit load ? i cc (note 3) v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 3. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 0.3 note: unit load is ? i cc limit speci?d in dc electrical speci?a- tions table, e.g., 360 a max at 25 o c. cd54hc109, cd74hc109, cd54hct109, CD74HCT109
5 prerequisite for switching speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types setup time j, k, to cp t su - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns hold time j, k, to cp t h -25--5-5-ns 4.5 5 - - 5 - 5 - ns 65--5-5-ns removal time r, s, to cp t rem - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns pulse width cp, r, st w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cp frequency f max - 2 6 - - 5 - 4 - mhz 4.5 30 - - 25 - 20 - mhz 6 35 - - 29 - 23 - mhz hct types setup time j, k to cp t su - 4.5 18 - - 23 - 27 - ns hold time j, k to cp t h - 4.5 3 - - 3 - 3 - ns removal time r, s, to cp t rem - 4.5 18 - - 23 - 27 - ns pulse width cp, r, st w - 4.5 18 - - 23 - 27 - ns cp frequency f max - 4.5 27 - - 22 - 18 - mhz switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, cp q, q t plh , t phl c l = 50pf 2 - - 175 - 220 - 265 ns c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - ----ns c l = 50pf 6 - - 30 - 37 - 45 ns propagation delay, s q t plh , t phl c l = 50pf 2 - - 120 - 150 - 180 ns c l = 50pf 4.5 - - 24 - 30 - 36 ns c l = 15pf 5 - 9 - ----ns c l = 50pf 6 - - 20 - 26 - 31 ns propagation delay, s q t plh , t phl c l = 50pf 2 - - 155 - 195 - 235 ns c l = 50pf 4.5 - - 31 - 39 - 47 ns c l = 15pf 5 - 13 - ----ns c l = 50pf 6 - - 26 - 33 - 40 ns cd54hc109, cd74hc109, cd54hct109, CD74HCT109
6 propagation delay, r q t plh , t phl c l = 50pf 2 - - 185 - 230 - 280 ns c l = 50pf 4.5 - - 37 - 46 - 56 ns c l = 15pf 5 - 15 - ----ns c l = 50pf 6 - - 31 - 39 - 48 ns propagation delay, r q t plh , t phl c l = 50pf 2 - - 170 - 215 - 255 ns c l = 50pf 4.5 - - 34 - 43 - 51 ns c l = 15pf 5 - 14 - ----ns c l = 50pf 6 - - 29 - 37 - 43 ns transition time t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns c l = 50pf 4.5 - - 15 - 19 - 22 ns c l = 50pf 6 - - 13 - 16 - 19 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max c l = 15pf 5 - 60 - ----mhz power dissipation capacitance (notes 4, 5) c pd - 5-30-----pf hct types propagation delay, cp q, q t plh , t phl c l = 50pf 4.5 - - 40 - 50 - 60 ns c l = 15pf 5 - 17 - ----ns propagation delay, s q t plh , t phl c l = 50pf 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - ----ns propagation delay, s q t plh , t phl c l = 50pf 4.5 - - 45 - 56 - 68 ns c l = 15pf 5 - 19 - ----ns propagation delay, r q t plh , t phl c l = 50pf 4.5 - - 45 - 56 - 68 ns c l = 15pf 5 - 19 - ----ns propagation delay, r q t plh , t phl c l = 50pf 4.5 - - 37 - 46 - 56 ns c l = 15pf 5 - 15 - ----ns transition time (figure 5) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max cl = 15pf 5 - 54 - ----mhz power dissipation capacitance (notes 4, 5) c pd - 5-33-----pf notes: 4. c pd is used to determine the dynamic power consumption, per flip-flop. 5. p d = c pd v cc 2 f i + c l f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd54hc109, cd74hc109, cd54hct109, CD74HCT109
7 test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 7. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 8. hct clock pulse rise and fall times and pulse width figure 9. hc and hcu transition times and propaga- tion delay times, combination logic figure 10. hct transition times and propagation delay times, combination logic figure 11. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 12. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = f cl i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc109, cd74hc109, cd54hct109, CD74HCT109
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-9070101mea active cdip j 16 1 none call ti level-nc-nc-nc cd54hc109f3a active cdip j 16 1 none call ti level-nc-nc-nc cd54hct109f3a active cdip j 16 1 none call ti level-nc-nc-nc cd74hc109e active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc109m active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim cd74hc109m96 active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim cd74hc109mt active soic d 16 250 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim CD74HCT109e active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc CD74HCT109m active soic d 16 40 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim CD74HCT109m96 active soic d 16 2500 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim CD74HCT109mt active soic d 16 250 pb-free (rohs) cu nipdau level-2-260c-1 year/ level-1-235c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 28-feb-2005 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated
|
